---------------------------------------------------------------- | | | | | Zilog | | | | ZZZZZZZ 88888 000 000 1 | | Z 8 8 0 0 0 0 11 | | Z 8 8 0 0 0 0 0 0 1 | | Z 88888 0 0 0 0 0 0 1 | | Z 8 8 0 0 0 0 0 0 1 | | Z 8 8 0 0 0 0 1 | | ZZZZZZZ 88888 000 000 111 | | | | Z8001 MICROPROCESSOR Instruction Set Summary | | | | _________ _________ | | _| \__/ |_ | | <--> AD0 |_|1 48|_| AD8 <--> | | _| |_ | | <--> AD9 |_|2 47|_| SN6 --> | | _| |_ | | <--> AD10 |_|3 46|_| SN5 --> | | _| |_ | | <--> AD11 |_|4 45|_| AD7 <--> | | _| |_ | | <--> AD12 |_|5 44|_| AD6 <--> | | _| |_ | | <--> AD13 |_|6 43|_| AD4 <--> | | ____ _| |_ | | --> STOP |_|7 42|_| SN4 --> | | __ _| |_ | | --> Mi |_|8 41|_| AD5 <--> | | _| |_ | | <--> AD15 |_|9 40|_| AD3 <--> | | _| |_ | | <--> AD14 |_|10 39|_| AD2 <--> | | _| |_ | | +5V |_|11 38|_| AD1 <--> | | __ _| |_ | | --> VI |_|12 Z8001 37|_| SN2 --> | | ___ _| |_ | | --> NVI |_|13 36|_| GND | | ____ _| |_ | | --> SEGT |_|14 35|_| CLOCK <-- | | ___ _| |_ __ | | --> NMI |_|15 34|_| AS --> | | _____ _| |_ | | --> RESET |_|16 33|_| RESERVED | | __ _| |_ _ | | <-- Mo |_|17 32|_| B/W --> | | ____ _| |_ _ | | <-- MREQ |_|18 31|_| N/S --> | | __ _| |_ _ | | <-- DS |_|19 30|_| R/W --> | | _| |_ _____ | | <-- ST3 |_|20 29|_| BUSAK --> | | _| |_ ____ | | <-- ST2 |_|21 28|_| WAIT <-- | | _| |_ _____ | | <-- ST1 |_|22 27|_| BUSRQ <-- | | _| |_ | | <-- ST0 |_|23 26|_| SN0 --> | | _| |_ | | <-- SN3 |_|24 25|_| SN1 --> | | |______________________| | | | | | |Written by Jonathan Bowen | | Programming Research Group | | Oxford University Computing Laboratory | | 8-11 Keble Road | | Oxford OX1 3QD | | England | | | | Tel +44-865-273840 | | | |Created October 1981 | |Updated April 1985 | |Issue 1.2 Copyright (C) J.P.Bowen 1985| ---------------------------------------------------------------- ---------------------------------------------------------------- |Mnemonic |CZSPDH|Description |Notes | |------------+------+----------------------------+-------------| |ADCb d,s |****bb|Add with Carry |d=d+s+C | |ADDa d,s |****bb|Add |d=d+s | |ANDb d,s |-**b--|Logical AND |d=d&s | |BITb d,s |-*----|Bit Test |Z=~d | |CALL d |------|Call |-[SP]=PC,PC=d| |CALR d |------|Call Relative |-[SP]=PC,PC=d| |CLRb d |------|Clear |d=0 | |COMb d |-**b--|Complement |d=~d | |COMFLG f |++++--|Complement Flag |f=~f | |CPa d,s |****--|Compare |d-s | |CPDb d,s,c|?*?*--|Compare and Decrement |d-s,r=r-1 | |CPDRb d,s,c|?*?*--|Compare, Decrement and Rept |CPD till r=0 | |CPIb d,s,c|?*?*--|Compare and Increment |d-s,r=r+1 | |CPIRb d,s,c|?*?*--|Compare, Increment and Rept |CPI till r=0 | |CPSDb d,s,c|?*?*--|Compare String and Decrement|d-s,r=r-1 | |CPSDRb d,s,c|?*?*--|Compare String, Dec. and Rep|CPSD till r=0| |CPSIb d,s,c|?*?*--|Compare String and Increment|d-s,r=r+1 | |CPSIRb d,s,c|?*?*--|Compare String, Inc. and Rep|CPSI till r=0| |DAB d |***---|Decimal Adjust Byte |d=BCD format | |DECb d,s |-***--|Decrement (s=1-16) |d=d-s | |DI i |------|Disable Interrupts | #| |DIVl d,s |****--|Divide |d=d/s | |DbJNZ r,d |------|Decrement & Jump if Not Zero|r=r-1 | |EI i |------|Enable Interrupts | #| |EXb d,s |------|Exchange |d<->s | |EXTSa d |------|Extend Signs | | |HALT |------|Halt | #| |pINb d,s |------|(Special) Input |d=s #| |INCb d,s |-***--|Increment (s=1-16) |d=d+s | |pINDb d,s,r|---*--|(Special) Input and Dec. |d=s,r=r-1 #| |pINDRb d,s,r|---1--|(Special) Input, Dec. & Rept|IND till r-0#| |pINIb d,s,r|---*--|(Special) Input and Inc. |d=s,r=r+1 #| |pINIRb d,s,r|---1--|(Special) Input, Inc. & Rept|INI till r=0#| |IRET |??????|Interrupt Return |PS=[SP]+ #| |JP cc,d |------|Jump |PC=d | |JR cc,d |------|Jump Relative |PC=d | |LDa d,s |------|Load |d=s | |LDA d,s |------|Load Address |d=EAs | |LDAR d,s |------|Load Address Relative |d=EAs | |LDCTL d,s |++++++|Load Control |d=s #| |LDCTLB d,s |++++++|Load Control Byte |d=s | |LDDb d,s,r|---*--|Load and Decrement |d=s,r=r-1 | |LDDRb d,s,r|---1--|Load, Decrement and Repeat |LDD till r=0 | |LDIb d,s,r|---*--|Load and Increment |d=s,r=r+1 | |LDIRb d,s,r|---1--|Load, Increment and Repeat |LDI till r=0 | |LDK d,s |------|Load Constant (s=0-15) |d=s | |LDM d,s,n|------|Load Multiple (n=1-16) |d=s (n words)| |LDPS s |??????|Load Program Status |PS=s #| |LDRa d,s |------|Load Relative |d=s | |MBIT |??*???|Multi-Micro Bit Test |S=~MI pin #| |MREQ d |-**---|Multi-Micro Request |S=available #| |MRES |------|Multi-Micro Reset |~MI=high #| |MSET |------|Multi-Micro Set |~MO=low #| |MULTl d,s |***0--|Multiply |d=d*s | |NEGb d |****--|Negate |d=-d | |NOP |------|No Operation | | |ORb d,s |-**b--|Logical inclusive OR |d=dvs | |pOTDRb d,s,r|---1--|(Special) Output, Dec. & Rep|OTD till r=0#| |pOTIRb d,s,r|---1--|(Special) Output, Inc. & Rep|OTI till r=0#| |pOUTb d,s |------|(Special) Output |d=s #| |pOUTDb d,s,r|---*--|(Special) Output and Dec. |d=s,r=r=1 #| |pOUTIb d,s,r|---*--|(Special) Output and Inc. |d=s,r=r+1 #| |POPl d,s |------|Pop |d=s,[EAs]+ | |PUSHl d,s |------|Push |-[EAs],d=s | |RESb d,s |------|Reset Bit |d=0 | |RESFLG f |++++--|Reset Flag |f=0 | |RET cc |------|Return |PC=[SP]+ | |RLb d,s |****--|Rotate Left |d=d<-s | |RLCb d,s |****--|Rotate Left through Carry |d={C,d}<-s | |RLDB ll,s |-*?---|Rotate Left Digit Byte |s={ll,s}<-4 | |RRb d,s |****--|Rotate Right |d=s->d | |RRCb d,s |****--|Rotate Right through Carry |d=s->{C,d} | |RRDB ll,s |-*?---|Rotate Right Digit Byte |s=4->{ll,s} | |SBC d,s |****bb|Subtract with Carry |d=d-s-C | |SC s |------|System Call (-[SP]={PS,ins})|PS=sys PS #| |SDAa d,s |****--|Shift Dynamic Arithmetic |d={1,d,0}<-s | ---------------------------------------------------------------- ---------------------------------------------------------------- |Mnemonic |CZSPDH|Description |Notes | |------------+------+----------------------------+-------------| |SDLa d,s |***?--|Shift Dynamic Logical |d={0,d,0}<-s | |SETb d,s |------|Set Bit |d=1 | |SETFLG f |++++--|Set Flag |f=1 | |SLAa d,s |****--|Shift Left Arithmetic |d={d,0}<-s | |SLLa d,s |***?--|Shift Left Logical |d={d,0}<-s | |SRAa d,s |***0--|Shift Right Arithmetic |d=s->{1,d} | |SRLa d,s |***?--|Shift Right Logical |d=s->{0,d} | |SUBa d,s |****bb|Subtract |d=d-s | |TCCb cc,d |------|Test Condition Code |If cc d<0>=1 | |TESTa d |-***--|Test |dv0 | |TRDB d,s,r|-?-*--|Translate and Decrement |d=s[d],r=r-1 | |TRDRB d,s,r|-?-1--|Translate, Dec. and Repeat |TRDB till r=0| |TRIB d,s,r|-?-*--|Translate and Increment |d=s[d],r=r+1 | |TRIRB d,s,r|-?-1--|Translate, Inc. and Repeat |TRIB till r=0| |TRTDB s,s,r|-*-*--|Translate, Test and Dec. |RH1=s2[s1],..| |TRTDRB s,s,r|-*-*--|Translate, Test, Dec. & Rept|TRTDB till...| |TRTIB s,s,r|-*-*--|Translate, Test and Inc. |RH1=s2[s1],..| |TRTIRB s,s,r|-*-*--|Translate, Test, Inc. & Rept|TRTIB till...| |TSETb d |--*---|Test and Set |{S,d}=d | |XOR d,s |-**b--|Logical Exclusive OR |d=dxs | |------------+------+----------------------------+-------------| | FCW |-*01? |Unaffected/affected/reset/set/unknown | | |+b |Optionally affected/affected for byte only| | C |C |Carry flag (Bit 7) | | Z | Z |Zero flag (Bit 6) | | S | S |Sign flag (Bit 5) | | D | D |Decimal adjust flag (Bit 4) | | P/V | P |Parity/Overflow flag (Bit 3) | | H | H|Half carry flag (Bit 2) | |-------------------+------------------------------------------| | #n #nn #nnnn |Immediate data mode (IM, 4/8/16/32-bit) | | r |Register addressing mode (R) | | @r |Indirect Register mode (IR) | | <>nn nn |nn| |Direct Addressing mode (DA) | | <>nn[Rn] nn[Rn]|Indexed Addressing mode (X, not R0) | | $+nn nn |Relative Addressing mode (RA) | | RRn[#nn] |Based Addressing mode (BA, not RR0) | | RRn[Rn] |Based Indexed addressing mode (BX, not R0)| |-------------------+------------------------------------------| |AVAL nnnn(,...) |Define Address Value(s) | |BVAL n(,...) |Define Byte Value(s) | |EVEN |Set program counter to Even address | |LVAL nnnn(,...) |Define Long word Value(s) | |WVAL nn(,...) |Define Word Value(s) | |-------------------+------------------------------------------| | FCW |Flag Control Word (16-bit) | | PC |Program Counter (32-bit) | | PSAP |Program Status Area Pointer (32-bit) | | REFRESH |Refresh control register (16-bit) | | RLn |Low byte register (8-bit, n=0-7) | | RHn |High byte register (8-bit, n=0-7) | | Rn |Word register (16-bit, n=0-15) | | RRn |Double word register (32-bit, n=0-14,even)| | RQn |Quadruple word reg. (64-bit, n=0/4/8/12) | | RR14 |Used as stack pointer (32-bit) | |-------------------+------------------------------------------| | a |Blank, B or L (Word/Byte/Long operation) | | b |Blank or B (Word/Byte operation) | | c |Condition (r,cc) | | cc |Condition Code (F/Z/NZ/C/NC/PL/MI/NE/EQ/ | | | OV/NOV/PE/PO/GE/LT/GT/LE/UGE/ULT/UGT/ULE)| | d d |Destination/Bit X of Destination | | f |Flag(s) (C/Z/S/P/V) | | i |Interrupt (VI/NVI) | | l |Blank or L (Word/Long word operation) | | ll |Link Location (bottom 4 bits of register) | | n nn nnnn |Constant expression (8/16/32-bit) | | p |Blank or S (Normal/Special operation) | | r |Register (RLn/RHn/Rn/RRn/RQn) | | s EAs |Source/Effective Address of Source | | + - * / |Arithmetic add/subtract/multiply/divide | | & ~ v x |Logical AND/NOT/inclusive OR/exclusive OR | | <-X X-> |Rotate left/right by X bits | | [ ] [ ]+ -[ ] |Indirect address/auto-increment/decrement | | { } # |Combination of operands/privileged instr. | | <> |nn| |Segment/short offset (0-255) | ----------------------------------------------------------------